The IntelliProp IPC-GZ198A-ZM Gen-Z Link Layer is an IP Core that allows companies to build Gen-Z compliant devices. The IPC-GZ198A-ZM is compliant with the Gen-Z 1.1 Core specification and provides support for the Link Local protocol and passing of end-to-end packets. The IPC-GZ198A-ZM IP core is designed for integration into FPGA and ASIC developments to minimize development time and familiarization required to develop this IP independently. The IPC-GZ198A-ZM is fully verified in pseudo random simulation.
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Applications for the Gen-Z Link Layer IP Core include
- Requester/Responder/Switch components on a Gen-Z Fabric
IPC-GZ198A-ZM Features
- Full Verilog/SystemVerilog core
- Compliant with the Gen-Z 1.1 Core Specification
- Explicit Link Local Flow Control credit management
- Variable PHY_TXDATAREQ latency acceptance
- Multiple Virtual Channel buffering with dynamic receive buffer allocation
- Dynamic congestion based Virtual Channel re-mapping
- Transient/Non-Transient error detection, handling and recovery
- Explicit OpClass end-to-end traffic support
- Link-Level Reliability
Provided with the Gen-Z Link Layer IP Core
| Documentation: | Comprehensive User Documentation |
| Design File Formats: | Encrypted Verilog/SystemVerilog |
| Constraints Files: | Provided per FPGA |
| Verification: | ModelSim verification model |
| Instantiation Templates: | Verilog |
| Reference Designs & Application Notes: | Synthesis and place and route scripts |
| Additional Items: | none |
| Simulation Tool Used: | ModelSim (contact IntelliProp for latest versions supported) |
| Support: | The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date. |
| Notes: | Other simulators are available. Please contact IntelliProp for more information. |
Functional Description
The IPC-GZ198A-ZM Gen-Z Link Layer IP Core provides a streaming interface to extract and inject end-to-end Gen-Z packets into a Gen-Z fabric. The Link Layer IP Core will consume and produce all Link Local Packets transferred between a peer Gen-Z Link Layer.
The Link Protocol is entirely abstracted away from the user enabling a simpler packet handling scheme in upper layers. All Link sequences including Link initialization, Link Flow Control, Link Synchronization, Transient error detection and handling, etc. are managed autonomously by internal state machines.
The Gen-Z Link Layer IP Core exposes several synthesis time parameters and a memory-mapped register interface for static and dynamic configuration flexibility.