The IntelliProp IPC-BL120A-ZM is an AES-XTS Encryption Core supporting 128 or 256 bit encryption. The IPC-BL120A-ZM provides encryption/decryption based on a design principle known as substitution-permutation network (SP-network). An SP-network takes a block of the plaintext (clear data or non-encrypted data) and the key as inputs, and applies several alternating “rounds” or “layers” of substitution boxes and permutation boxes to produce the ciphertext (encrypted data). The IPC-BL120A-ZM is fully verified in pseudo random simulation.
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AES-XTS Encryption core Applications
- Applications that require integration into the data path to provide encryption/decryption of data
- Applications where high levels of encryption are required
- Applications requiring FIPS-197 certified encryption/ decryption algorithms
- Applications that require very high throughput and an encryption solution that has minimal impact on throughput
IPC-BL120-ZM Features
- Full Verilog core
- 128 or 256 bit selectable AES encryption
- The AES-XTS algorithm is FIPS-197 certified, cert. no 2408.
- The encode and decode channels are made to look and act like independent FIFOs for ease of integration. The control block has a register interface to be easily managed by a hardware state machine or controlled by a processor for operations such as key initialization, and TWEAK configuration and management.
- Programmable number of pipeline paths allows the user to balance area/bandwidth requirements. The number of parallel pipelines can be configured to support high performance/high throughput applications as well as lower performance and/or resource limited applications.
- The core has a simulation test bench and register initialization sequence to support rapid integration
- Processor and RTL control interface
- Independent Cipher/Inverse Cipher key management
- Concurrent encode and decode support
- Bypass functionality to send data through the Core unmodified
- Supports integer multiples of 16 byte Data Unit sizes
AES-XTS Encryption IP Core
| Documentation: | Comprehensive User Documentation |
| Design File Formats: | Encrypted Verilog |
| Constraints Files: | Provided per FPGA |
| Verification: | ModelSim verification model |
| Instantiation Templates: | Verilog |
| Reference Designs & Application Notes: | Synthesis and place and route scripts |
| Additional Items: | Simulation Script, Sample Vectors, Testbench |
| Simulation Tool Used: | ModelSim (contact IntelliProp for latest versions supported) |
| Support: | The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date. |
| Notes: | Other simulators are available. Please contact IntelliProp for more information. |
Functional Description
The IPC-BL120A-ZM is an IP core that is an encoder/decoder that allows the user to provide full disk encryption for their storage device. The IPC-BL120A-ZM supports AES-XTS with an option for 128 or 256 bit encryption levels and is capable of data throughput that supports SATA 6 Gb/s speed, SAS 12 Gb/s, and PCIe (NVMe) Gen4 x4 lanes. The encryption algorithm used in the IPC-BL120A-ZM is FIPS-197 certified.