The IPC-BL157-ZM, Advanced Flash Controller Interface (AFCI) is a register level interface that allows software and hardware state machines the ability to communicate with a nonvolatile memory subsystem. The command communication, data movement, and status information are accomplished with a minimal number of non-cacheable read/writes. This is important to maximize throughput and minimize impact of register read/writes to the platform software.
Command information is managed utilizing a command submission and completion queue architecture which uses doorbell registers in the controller register set to communicate that a new command has been populated in the command queue. This queue is a circular buffer which can be as small as a depth of 2 and as large as a depth of 65536. This flexibility is important to manage system platform trade-offs of performance with system complexity.
Administrative commands are communicated using a secondary command submission and completion queue. This allows for two completely separate masters to issue command information to the controller. The intention here is to allow for the main data command information to use the command submission queue, and administrative/maintenance commands to be issued using the administrative queue. The arbitration scheme between the admin queue and the command queue can be set by system software.
Optional Configuration
- Embedded AES-XTS Encryption
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Advanced Flash Controller Interface (AFCI) core Applications
- Embedded applications that require communication with NAND arrays
- NVDIMM applications
- Solid State Disk (SSD) controllers
- Any system requiring communication with persistent storage
IPC-BL157-ZM Features
- Multi-Port Architecture allows connecting up to 32 NAND devices (128 total NAND targets)
- Separate Administrative and I/O queues for flexible datapath management
- Maximum of 1 register write per command submission/ completion
- Industry standard bus interface (AXI-4) master used for command fetching, command completion, and data movement
- Support for up to 64k commands per command queue
- Independent R/W channels allow data movement from system to NAND and NAND to system concurrently
- Actively maintains a command per NAND LUN for maximum throughput to/from the NAND
- Automatic training sequence performed on a per-chip-enable basis
- Firmware selectable taps for quick speed change via Set Features command
- Selectable BCH-ECC correction capabilities based on NAND selection
- Supports ONFI 3.2 and 4.0 compliant TLC, MLC and SLC NAND
- Supports NV-DDR, NV-DDR2, Toggle 2.0
- Optional: AES-XTS 256 bit encryption (P/N: IPC-BL157A-1-ZM)
- The optionally available AES-XTS encryption algorithm is FIPS-197 certified, cert. no. 2408
Provided with the NVMe Host Accelerator IP Core
| Documentation: | Comprehensive User Documentation |
| Design File Formats: | Encrypted Verilog |
| Constraints Files: | Provided per FPGA |
| Verification: | ModelSim verification model |
| Instantiation Templates: | Verilog |
| Reference Designs & Application Notes: | Synthesis and place and route scripts |
| Additional Items: | Simulation Script, Sample Vectors, Sample Testbench, Reference Design |
| Simulation Tool Used: | ModelSim (contact IntelliProp for latest versions supported) |
| Support: | The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date. |
| Notes: | Other simulators are available. Please contact IntelliProp for more information. |
Functional Description
The IPC-BL157A-ZM IP core is designed around a scalable port architecture which allows for parallel communication across a multitude of NAND devices. Each NAND port can be connected to one or more NAND Targets. The parallelized port architecture allows scalable capacity and performance to meet a wide variety of applications.
The IPC-BL157A-ZM is based on a paired Submission and Completion queue mechanism. The AFCI submission queue is a circular buffer where the producer of commands is either software or a hardware state machine external to the AFCI controller. The consumer of commands is the AFCI submission state machine. New command entries are reported to the AFCI submission state machine by a single, non-cacheable write to the AFCI controller registers. The command producer can arm as many commands as there is space in the command queue with a single register write.
The Advanced Flash Controller (AFCI) Interface core optionally supports AES-XTS under Part # IPC-BL157A-1-ZM and incorporates a 256 bit encryption level capable of data throughput greater than 20Gbps. The encryption algorithm used in the IPC-BL157A-1-ZM is FIPS-197 certified.