IPC-BL204A-ZM – AES-CTR Encryption IP Core

The IntelliProp IPC-BL204A-ZM is an AES-CTR (Counter Mode) Encryption Core supporting 128 or 256 bit encryption. The IPC-BL204A-ZM provides encryption/decryption based on a design principle known as substitution-permutation network (SP-network). An SP-network takes a block of the plaintext (clear data or non-encrypted data) and the key as inputs, and applies several alternating “rounds” or “layers” of substitution boxes and permutation boxes to produce the ciphertext (encrypted data). Counter Mode (CTR) is an extension upon the IntelliProp AES-ECB symmetric-key block-cipher to create a stream cipher that provides data confidentiality.

The IPC-BL204A-ZM is fully verified in pseudo random simulation. It is also compatible with OpenSSL’s AES-256-CTR cipher mode.

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IPC-BL204A-ZM AES-CTR Encryption core Applications

  • Applications that require integration into the data path to provide encryption/decryption and authentication of data streams
  • Applications where high levels of encryption are required
  • Applications that require very high throughput and an encryption solution that has minimal impact on throughput
  • Applications that require a streaming data interface such as network traffic

IPC-BL204A-ZM Features

  • Full Verilog core
  • Synth-time selectable number of parallel paths allows the user to balance area/bandwidth requirements
  • Synth-time selectable internal buffer sizing for area/bandwidth balancing
  • Synth-time selectable 128 or 256 bit AES encryption key size
  • Optional internal Hamming ECC protection/correction on internal memories
  • Multiple independent data streams for flexible run-time dynamic packet sizing
  • Key expansion caching for optimized performance of packets using repeated keys
  • Packet queuing ready, for optimal throughput
Intel FPGA Solutions Network
Xilinx
Provided with the IPC-BL204A-ZM AES-CTR Encryption IP Core
Documentation:Comprehensive User Documentation
Design File Formats:Encrypted Verilog
Constraints Files:Provided per FPGA
Verification:ModelSim verification model
Instantiation Templates:Verilog
Reference Designs & Application Notes:Synthesis and place and route scripts
Additional Items:Simulation Script, Sample Vectors, Testbench
Simulation Tool Used:ModelSim (contact IntelliProp for latest versions supported)
Support:The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date.
Notes:Other simulators are available. Please contact IntelliProp for more information.

Functional Description

The IPC-BL204A-ZM is an IP core that is an encoder/decoder that allows the user to do packet or data stream encryption/decryption. The IPC-BL204A-ZM supports AES-CTR with an option for 128 or 256 bit key encryption levels and is capable of data throughput that supports SATA 6 Gb/s speed, SAS 12 Gb/s, PCIe (NVMe) Gen4 x4 lanes, 10Gb/s and 25Gb/s Ethernet.