The IntelliProp IPC-GZ190A-HI Gen-Z Requester is an IP Core that allows companies to build Gen-Z compliant Requester devices. The IPC-GZ190A-HI is compliant with the Gen-Z 1.1 Core Specification and provides support for all OpCodes and OpClasses falling under the Explicit OpClass packet format. The IPC-GZ190A-HI IP core is designed for integration into FPGA and ASIC developments to minimize development time and familiarization required to develop this IP independently. The IPC-GZ190A-HI is fully verified in pseudo random simulation.
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Applications for the Gen-Z Requester IP Core include
- Applications that require an industry compliant Gen-Z Requester interface
- Requester devices attaching to a Gen-Z Fabric or directly to a Gen-Z Device
IPC-GZ190-HI Features
- Full Verilog/SystemVerilog core
- Compliant with the Gen-Z 1.1 Core Specification
- Explicit OpClass support (Core64, Control and Atomic, etc.)
- Non-idempotent Atomic operation handshake support (NIRR/NIRR Ack)
- AXI-Stream and AXI-MM system interconnects
- Avalon-ST and Avalon-MM system interconnects
- Multi-link Layer support
- Request timeout and retry handling
Provided with the Gen-Z Requestor IP Core
| Documentation: | Comprehensive User Documentation |
| Design File Formats: | Encrypted Verilog/SystemVerilog |
| Constraints Files: | Provided per FPGA |
| Verification: | ModelSim verification model |
| Instantiation Templates: | Verilog |
| Reference Designs & Application Notes: | Synthesis and place and route scripts |
| Additional Items: | none |
| Simulation Tool Used: | ModelSim (contact IntelliProp for latest versions supported) |
| Support: | The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date. |
| Notes: | Other simulators are available. Please contact IntelliProp for more information. |
Functional Description
The IPC-GZ190A-HI Gen-Z Requester IP Core provides a system attached fabric interface for sending and receiving end-to-end Gen-Z packets. The Requester IP Core can be directly attached to the Link Layer IP Core or attached to an internal switch that connects multiple Requester, Responder, or Link Layer IP Cores.
The Requester can be dynamically configured to route different packet OpCode and OpClass combinations over multiple streaming or memory-mapped interfaces allowing flexibility in handling methods for requests and responses. Packet consumption or generation through the system interfaces can be handled by either user logic state machines or by an embedded processor.