The IntelliProp IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe is an IP Core that allows companies to attach a Gen-Z core to a PCIe Phy. The IPC-GZ197A-ZM is compliant with the Gen-Z 1.1 Physical Layer Specification and provides support for multi-lane links, lane reversal, and link width reduction. The IPC-GZ197A-ZM IP Core is designed for integration into FPGA and ASIC developments to minimize development time and familiarization required to develop this IP independently. The IPC-GZ197A-ZM is fully verified in pseudo random simulation.
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Applications for the Gen-Z Physical Layer IP Core include
- Applications that require communication of an industry compliant Gen-Z device over PCIe Phy
IPC-GZ197-ZM Features
- Full Verilog/SystemVerilog core
- Compliant with the Gen-Z 1.1 Physical Layer Specification
- Compliant with the Gen-Z 1.1 Physical Layer Abstraction interface
- Multi-lane symmetric link support up to 16 lanes per link
- Lane reversal and link width reduction support
- Flow control and Phy Idle injection
- Transient/Non-Transient error detection and reporting
- Software configurable core settings via a register interface
- PCIe Gen4 Phy speed (16Gbps)
Provided with the Gen-Z Physical Layer for PCIe IP Core
| Documentation: | Comprehensive User Documentation |
| Design File Formats: | Encrypted Verilog/SystemVerilog |
| Constraints Files: | Provided per FPGA |
| Verification: | ModelSim verification model |
| Instantiation Templates: | Verilog |
| Reference Designs & Application Notes: | Synthesis and place and route scripts |
| Additional Items: | none |
| Simulation Tool Used: | ModelSim (contact IntelliProp for latest versions supported) |
| Support: | The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date. |
| Notes: | Other simulators are available. Please contact IntelliProp for more information. |
Functional Description
The IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe provides a Gen-Z 0.5d Physical Layer Specification compliant Physical Layer Abstraction interface for Gen-Z communication over a PCIe Phy. The IP core is scalable to support up to 16 lanes in a single link and most PLA data widths. The IntelliProp Bus Interface connection to the Transceiver Wrapper allows for register configurable transmitter and receiver equalization settings of the transceivers. The IP core manages initialization and configuration of the transceivers as well as striping and scrambling/descrambling of link layer data over the PLA interface.