The IntelliProp IPC-NV163-DT IP core is an industry standard NVMe target IP core that allows companies to build high speed NVMe based storage products. The IPC-NV163-DT provides a hardware accelerated queue management interface for NVMe commands and completions as well as provides the NVMe controller register interface for host communication and controller management.
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IPC-NV163-DT NVMe Target Core Applications
The IPC-NV163-DT is available for integration into FPGA or ASIC designs to provide an industry compliant NVMe. Target applications for the IPC-NV163-DT include:
- NVMe SSD Controllers
- NVMe fabric devices
- NVMe Bridge Systems
IPC-NV163-DT NVMe Target Core Features
- Fully compliant to the NVM Express 1.4 industry specification
- Compliant with 3rd party PCIe Target IP cores
- Application layer (command based) interface with Processor interface
- Data Interface through FIFOs
- Processor interface for register access
- Command interrupts for user processing system
- Synthesis time maximum queue depths of up to 64k supported
- Supports up to 8k queues
- Automated PCIe interrupt generation on posting of completions
- Synchronous design for easy integration
NVMe Target IP Core
| Documentation: | Comprehensive User Documentation |
| Design File Formats: | Encrypted Verilog |
| Constraints Files: | Provided per FPGA |
| Verification: | ModelSim verification model |
| Instantiation Templates: | Verilog (VHDL wrappers available) |
| Reference Designs & Application Notes: | Synthesis and place and route scripts |
| Additional Items: | Reference Design |
| Simulation Tool Used: | ModelSim (contact IntelliProp for latest versions supported) |
| Support: | The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date. |
| Notes: | Other simulators are available. Please contact IntelliProp for more information. |
Functional Description
The IPC-NV163-DT is designed to be integrated into an NVMe-compliant device application. The NVMe Target IP core manages multi-queue command fetching and completion posting via an internal controller register interface. Multi-queue command fetching is automated by state-machines internal to the IP core. As commands are fetched from host memory, the commands are filtered by type and provided to the controller application software via a simple context FIFO interface. As the controller application software completes command processing, the controller application software can complete the command via a simple completion context interface in the IP core. Once a completion context push is made to the IP core completion FIFO, the IP core internal state-machines automate the NVMe completion queue context transfer and update all pointer and phase information without software intervention. This automated command fetching and completion posting interface provides very low latency interface to the controller application software which is required for maximum IOPs and data bandwidth.