The IntelliProp SATA Bridge Platform is an extensible IP Core which encompasses a SATA Device core, a SATA Host core, along with an embedded processor to handle bridging between these cores including system management interfaces outside of SATA scope. The bridging interface allows for data and command manipulation along with non-host initiated command generation and processing to the attached SATA device. The negotiated transfer rate of each SATA connection is independent of the other SATA connections allowing SATA 1.5Gb/s, SATA 3Gb/s, and SATA 6Gb/s hosts and devices to communicate at their maximum rates, or lower rates to minimize power consumption.
Optional Configurations
- Embedded AES-XTS in the SATA AHCI core
- Hardware datapath for improved performance
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SATA Bridge Platform – IPP-SA143-BR core Applications
The IPP-SA143-BR is available for integration into device FPGA and ASIC designs to provide an industry compliant SATA 1.5 Gb/s, SATA 3.0 Gb/s, and SATA 6.0 Gb/s interface. Applications include:
- Customers can control the flow of commands and reorder queues, for example write blocking.
- Encryption bridge
- Compression of data whereby less space is utilized on the drive
- Allows for SATA-ATA devices to seamlessly represent themselves as SATA-ATAPI devices.
IPP-SA143-BR Features
- Fully compliant to SATA 1.5Gb/s, 3Gb/s, and 6Gb/sspecifications (SATA 3.3).
- Independent host and device SATA speed negotiation.
- Software extensible bridging platformCommand set support for Windows, along with standard Linux discovery and communication.
- Boot Device Capable.
- Firmware Extensions to allow support for Drive Letter Persistence as a Removable Device.
- Vendor Specific Command support (managed by firmware, supported in hardware).
- Supports Safe Eject Handling.
- Supports Write Protect Function Handling.
- Optional Hardware Datapath (IPP-SA143A-1-BR)
- Optional AES-XTS Encryption (IPP-SA143A-2-BR)
Provided with the SATA Bridge Platform Core
| Documentation: | Comprehensive User Documentation |
| Design File Formats: | Encrypted Verilog |
| Constraints Files: | Provided per FPGA |
| Verification: | ModelSim verification model |
| Instantiation Templates: | Verilog (VHDL wrappers available) |
| Reference Designs & Application Notes: | Synthesis and place and route scripts |
| Additional Items: | Simulation Script, Sample Vectors, Reference Design |
| Simulation Tool Used: | ModelSim (contact IntelliProp for latest versions supported) |
| Support: | The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date. |
| Notes: | Other simulators are available. Please contact IntelliProp for more information. |
Functional Description
The IPP-SA143-BR is designed to be connected to a SATA-compliant device and SATA-compliant host PC to send and receive Out of Band (OOB) signals, primitives and SATA Frame Information Structures (FIS). The SATA ADCI Core and SATA AHCI Core of the SATA Bridge Platform interface to the system via memory mapped register sets for command and data control by the processor subsystem and DMA engines for data movement. This allows for efficient data movement between a data buffer or system-attached FIFOs and the SATA Cores.